1. Field of the Invention
The present invention relates to a binary counter which is used in digital systems.
2. Description of the Prior Art
U.S. Pat. No. 4,002,926 discloses a static binary counter (FIG. 4) and its unit stage in CMOS (FIG. 5). As is well known, a static counter needs a large chip area on the integrated circuit and consumes a large amount of power because of its complicated construction. On the other hand, a dynamic binary counter is commonly used, in the high frequency range of more than 10 KHz, because of its simple construction. However, it is difficult to construct digital systems using only the dynamic counters. An increase in power consumption necessitates an electrical power source of large capacity. Also, the lifetime of a source such as the dry battery in a portable instrument is shortened, and the high power consumption increases the amount of heat produced in the circuit components. This lowers the reliability of the instrument and also prevents miniaurization of the package into a onechip LSI.